module BMX(out, x2, a, s, m1, m0);
output out;input x2, a, s, m1, m0;reg out;wire [2:0] mux_w;
assign mux_w = {x2, a, s};
always @(mux_w or m1 or m0) case(mux_w) 3'b010 : out = ~m1; 3'b001 : out = m1; 3'b110 : out = ~m0; 3'b101 : out = m0; 3'b011 : out = 0; 3'b111 : out = 0; 3'b000 : out = 1; 3'b100 : out = 1; endcase
endmodule
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