[OpenRisc]关于orpsocv2用makefile调用modelsim仿真的问题

不知大哦这样make多不对
仿真的时候就停了，没有反应，transcript也没有error
$[60] ->make .PHONY

### Compiling Verilog design library ###


### Compiling testbench ###

** Warning: (vlog-2103) Directory "/home/Jack/work/orpsocv2/sim/bin/../../sim/src" for -y option not found.
** Warning: /home/Jack/work/orpsocv2/sim/bin/../../rtl/verilog/ram_wb/ram_wb_b3.v(246): Function has no return value assignment.

### Launching simulation ###

Reading /home/Jack/eda_tools/modelsim6.5f/modeltech/tcl/vsim/pref.tcl

# 6.5f

# vsim -do {set StdArithNoWarnings 1; run -all; exit} -c -quiet -suppress 8598 tb
# // ModelSim SE 6.5f Jun 16 2010 Linux 2.6.35-23-generic
# //
# // Copyright 1991-2010 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# set StdArithNoWarnings 1
# 1
# run -all
#
# * Starting simulation of ORPSoC RTL.
# * Test: or1200-simple
#
利用makefile生成的define文件如下：
test-define.v
`define RTL_SIM
`define SIMULATOR_ICARUS
`define TEST_NAME_STRING "or1200-simple"
`define PROCESSOR_MONITOR_ENABLE_LOGS

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